1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to output driver circuitry within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. Within such communication systems, there are often interfaces between communication devices, integrated circuits, boards, and/or other elements therein. Sometimes, a last element (e.g., in an integrated circuit) that outputs a signal to be transmitted to another element (e.g., to another integrated circuit via a printed circuit board) is referred to as an output driver. Sometimes, such output drivers need to deliver slightly more current than other elements within the integrated circuit (such as those that only communicate between various elements within the integrated circuit).
FIG. 2 illustrates an embodiment of a prior art common mode logic (CML) output driver 200. A conventional/prior art high speed output driver generally has a CML structure that includes a differential pair of transistors similar as shown in this diagram. Within such a prior art CML output driver 200, a pre-driver is typically also employed to drive the input differential signal, in/inb, before being provided to the CML structure shown that includes the two 50Ω load resistors coupled between the drains of the differential pair of transistors and VDD and the current supply providing the current Io to the coupled sources of the differential pair of transistors. It is noted, however, that the load impedances of the pre-driver need not necessarily be two 50Ω load resistors, and the current supply of the pre-driver need not necessarily be providing the current Io to the coupled sources of the differential pair of transistors of the pre-driver (e.g., the pre-driver's load resistors may have different impedance, and the pre-driver's current supply may provide a different current). Furthermore, it is noted that this typical use of a CML buffer for the pre-driver within the prior art CML output driver 200 introduces a relatively power consumptive component therein.
Typically, a 50Ω termination is used, and the prior art CML output driver 200 is externally AC coupled through a capacitor (two capacitors for differential signaling) and another 50Ω resistor. The power consumption of such a prior art CML output driver 200 is a function of the required output swing and does not scale with the advancement of process technology employed to manufacture integrated circuits. As a result, output driver power consumption is becoming a larger percentage of the total power of the integrated circuit. In addition, as the power supply voltage within various communication devices shrinks with newer processes (e.g., newer processes often try to operate using a lower power supply voltage), the return loss of such a prior art CML output driver 200 degrades. In addition, meeting the stringent S11 specifications becomes more and more difficult.
The prior art CML output driver 200 of this diagram provides a differential peak to peak swing equal to 50Ω×Io, where Io is the current provided from the current source coupled to the source-coupled node of the differential pair of transistors. In addition, due to AC coupling (provided by the two capacitors), the output high levels of the prior art CML output driver 200 are only VDD−12.5×Io (instead of VDD); The output lower levels of the prior art CML output driver 200 are VDD−37.5×Io (instead of VDD) [which corresponds to a differential peak to peak swing equal to 50Ω×Io].
This voltage drop pushes the differential pair of transistors out of the saturation region. To overcome this issue, structures such as common mode lifting blocks may be connected to the output nodes (e.g., those nodes of the drains of the differential pair of transistors that provide output signal outp/outn or AC coupled output signal outp′/outn′). The addition of such blocks (e.g., common mode lifting blocks), however, introduces more capacitance that not only slows down the operation of the prior art CML output driver 200 but also degrades return loss performance thereof (e.g., hurts the reflection coefficient, S11, that corresponds to power reflected from imperfections within such an electrical, or optical, system).
Considering FIG. 2, the on-chip DC voltages provided by the prior art CML output driver 200 are as follows:
VDC=VDD−((50Ω−Io)/2), where the second term ((50Ω−Io)/2) is the voltage drop across each 50Ω resistor.
As the power supply voltages of many communication devices continues to go down (e.g., in many handheld devices, or generally devices where reduction in energy/power consumption is sought), this reduction in voltage can push the differential pair of transistors employed in the prior art CML output driver 200 out of saturation. This can cause significant problems in operation, in that, the differential pair of transistors is now operating in (or close to operating in) its linear region. The gain consequently reduces, and a larger signal is then needed to turn the component on/off. Moreover, because the input signals provided in such a prior art CML output driver 200 are analog in nature, they generally consume a large amount of power, which is of course undesirable for devices in which a reduction of energy/power consumption is sought.
There continues to be a need in the art for better means of implemented output driver related technology, including addressing the need for lower power consumption within such output driver related technology.